1. Field of the Invention
The present invention relates to a non-volatile semiconductor memory device installed in a system LSI, more particularly to a technology for increasing an integration level in a memory cell array and alleviating restrictions on a rewriting operation.
2. Description of the Related Art
There is a memory cell array having an virtual ground array structure as conventional technology, which includes two structures according to a sense amplifier method and a two-transistor current differential detecting method.
Sense Amplifier Method
FIG. 7 shows a schematic structure of the conventional memory cell array according to the sense amplifier method. The memory cell array having the virtual ground array structure comprises a plurality of memory cells m, a plurality of word lines W and a plurality of bit lines B. The memory cells m are arranged in a matrix shape. Each of the memory cells m is denoted by indices (x,y) showing their positions in the matrix. Each of rows of the memory cells are integrally connected to the word lines W. For example, all of the memory cells in a first line from the memory cell m(1,1) to the memory cell m(1,N) are connected to the word line W1. Each column of the memory cells is connected to two bit lines comprising one of each on both sides of the column. For example, one sides (left) of all of the memory cells on the left column from the memory cell m(1,1) to the memory cell m(1,N) are connected to the bit line B1, while the other sides (right) thereof are connected to the bit line B2. The memory cell m(x,y) is thus connected to the word line Wy, bit lines Bx and Bx+1.
Therefore, a tapping process executed to the selected word line and the selected two bit lines adjacent to each other enables various processes to be executed to the memory cell connected to them. First, a source line and a drain bit line are connected to a voltage source for supplying a predetermined voltage level which is V1 (V1>0, approximately 1.5 volts in general), and thereby pre-charged to the predetermined voltage level V1. The voltage level V1 is selected in accordance with a plurality of parameters such as a characteristic of the memory cell and word-line voltage. The voltage level V1 is generally within the range of 1-2 volts.
In a reading operation, the source bit line is discharged to a ground potential, and the drain bit line is separated from the V1 voltage source and connected to a sense amplifier 52 via a decoder 51. The voltage level detected on the drain bit line is used for determining data contents of the read memory cell. The decoder 51 includes all of electronic units allocated between the selected memory cell and the sense amplifier 52.
Two-Transistor Current differential Detecting Method
Referring to FIG. 6, a constitution of a non-volatile semiconductor memory device recited in No. H06-268180 of the Japanese Patent Applications Laid-Open in which the two-transistor current differential detecting method is adopted is described. A drain D1, a source Sc and a drain D2 are arranged with intervals on a surface of a semiconductor substrate 21. Floating gates 32 and 42 are formed at upper parts of a region on the surface of the semiconductor substrate 21 between the source Sc and the drains D1 and D2 via tunnel oxide films 31 and 41. Gate oxide films 33 and 43 are further formed thereon, and control gates 34 and 44 are further formed thereon. A source line S0 is connected to the source Sc, and a word line W0 is connected to the control gates 34 and 44. A bit line B1 and a bit line B2 complementary to the bit line B1 (hereinafter, referred to as complementary bit line) are respectively connected to the drains D1 and D2. The bit line B1 and the bit line B2 complemented with the bit line B1 are connected to a differential amplifier (not shown) in the reading operation.
The source Sc, drain D1, floating gate 32, control gate 34 constitute an MOS transistor Q1, and the source Sc, drain D2, floating gate 42, control gate 44 constitute an MOS transistor Q2.
Next, an operation of the non-volatile semiconductor memory device is described.
When data “1” is written, for example, a power-supply voltage (for example, 5V) is applied to the bit line B1, and the ground potential is applied to the complementary bit line B2. Further a high voltage (for example, 12V) is applied to, word line W0, and the ground voltage is applied to the source line S0. Accordingly, hot electrons are generated in vicinity of the drain D1 and injected into the floating gate 32. At the time, the hot electrons are not injected into the floating gate 42 because the hot electrons are not generated in vicinity of the drain D2. The complementary data whose logic levels are inverted relative to each other are thus memorized in the transistors Q1 and Q2, and it becomes a state where the data “1” is written in the memory cell.
Adversely, in the case of writing “0” data, the voltages applied to the bit line B1 and the complementary bit line B2 are set to the ones contrary to the before-mentioned voltages. Then, the electrons are injected into the floating gate 42, while the electrons are not injected into the floating gate 32. As a result, the data “0” is written in the memory cell.
Next, assuming that it is in a state where the data “1” is written wherein the electrons are injected into the floating gate 32 and not injected into the floating gate 42, the reading operation at this time is described.
In the reading operation, the power-supply voltage (for example, 5V) is applied to the word line W0, a low voltage (2V) is applied to the bit line B1 and the complementary bit line B2, and the ground potential is applied to the source Sc. The foregoing bias puts the transistor Q1 in an OFF state, and there is no memory cell current flow between the source Sc and the drain D1. However, the transistor Q2 is in an ON state, and the memory cell current flows into between the source Sc and the drain D2.
On the contrary, the transistor Q1 is in the ON state, and the Q transistor Q2 is in the OFF state in the reading operation in writing the data “0”. The voltage drop in the bit line B1 or the complementary bit line B2 resulting from the memory cell current in the reading operation is detected by the differential amplifier connected to the bit line B1 and the complementary bit line B2 and thereby judged.
In order to erase the data, a high voltage (for example, 12V) is applied to the source line S0 and the ground voltage is applied to the word line W0. In this manner, the electrons that have been injected into the floating gates 32 and 42 are drawn into the drains D1 and D2 through a tunnel effect.
As described above, in the non-volatile semiconductor memory device according to the two-transistor current differential detecting method, the complementary data is memorized in the two transistors, and the data “1” or the data “0” is detected by carrying out the differential detection between the outputs of the two transistors when the data is read. Therefore, a larger potential difference in the signals supplied to the differential amplifier can be obtained in comparison to the non-volatile semiconductor memory device according to the sense amplifier method.
In the semiconductor memory device according to the sense amplifier method for reading the information based on the memory cell current, a constant current source or a constant voltage source (reference) previously set and the memory cell current are compared to each other. Therefore, it is necessary to clarify magnitude relation between the reference of the constant current or the constant voltage and a gate threshold voltage in order to set the gate threshold voltage of the memory cell. However, a characteristic of respective memory cell transistor in the memory cell array has a variation, which makes it difficult to control the gate threshold voltage to be constant. Therefore, a certain degree of variation width (margin) is conventionally allowed.
Due to the foregoing reason, it has to be enjoined with variations of all of the bits in order to set the margin of the variation amount of the gate threshold voltage necessary for the writing operation. However, it gives more influence on a time length of the writing operation as the variation amount of the gate threshold voltage necessary for the writing operation is larger. Further, in the case where wiring capacitances in a wiring from the memory cell transistor to the sense amplifier and a wiring from the constant current or constant voltage reference source to the sense amplifier are different, amount of the difference affecting the memory cell current has to be added to the margin.
In the non-volatile semiconductor memory device according to the two-transistor current differential detecting method, there is no restriction on the gate threshold voltage due to the variations of the memory cell transistors because the differential detection between the outputs of the two transistors is carried out. However, it requires two transistors in order to memorize one bit, an area efficiency of the device is deteriorated.
Further, when the information once written is rewritten, updated information is then written after the written information is erased, which is a disadvantage shared by the non-volatile semiconductor memory devices (flash memory) according to the both methods. In other words, Because the two steps of erasure and writing are required, an operation time is increased.
Further, in the case where two memories, which are a memory for storing programs and a memory for storing data such as a built-in micro-controller, are necessary, it has to prepare two memories which are differently configured depending on respective usages.